1. Field of the Invention
This invention relates to a semiconductor integrated circuit that is very reliable. More particularly, the invention relates to a semiconductor integrated circuit using short channel MOS transistors with an effective channel length of about 1 micron or less.
2. Description of the Prior Art
It is known that if the effective channel length of a MOS transistor is about 1 micron or less, the threshold voltage and conductance fluctuate because of the effects of hot carriers produced in the vicinity of the drain. What is meant here by "about 1 micron" is an effective channel length of 1.2 microns, which is the minimum dimension formable with current MOS technology. The above-mentioned fluctuation of the threshold voltage and conductance caused by hot-carriers is called the hot carrier problem. This phenomenon is very troublesome since it reduces the reliability of VLSI circuits (very large scale integrated circuits) using short channel transistors with an effective channel length of about 1 micron or less and a variety of measures have been tried in the past to counter it. For example, there have been attempts to form a MOS transistor with small threshold voltage fluctuation by controlling the drain's impurity concentration distribution. However, this method gives an improvement that is only of the order of ten at most and still fails to achieve satisfactory reliability.
It is known that MOS transistor deterioration due to hot carriers is worse as the substrate current is greater.
FIG. 1 is a circuit diagram of a conventional inverter with a CMOS structure. As is well-known, this inverter is one in which p channel and n channel MOS transistors 1 and 2 have their gates and drains connected to one another, an input signal N1 is supplied to the common gate and an output signal N2 is obtained at the common drain.
FIG. 2(a) is an operating timing waveforms showing the variation of the input and output signals N1, N2 in this conventional inverter and FIG. 2(b) is an operating timing waveforms showing the variation of the corresponding substrate current Isub. FIG. 3 is a characteristic waveforms in which input and output signals N1 and N2 have been rewritten in the plane of the gate-source voltage Vgs and drain-source voltage Vds and to which equivalent substrate current curves also have been added. Curve Moff in this characteristic graph of FIG. 3 is the Vgs-Vds locus when the transistor 2 changes from the on to the off state, curve Mon is the Vgs-Vds locus when the transistor 2 changes from the off to the on state and the other curves are the curves of the equivalent substrate current of the substrate current Isub.
When the input signal N1 in the inverter of FIG. 1 changes from a low level to a high level and the p channel MOS transistor 1 changes from on to off and the n channel MOS transistor 2 from off to on, a large substrate current flows, as shown in FIG. 2(b). The reason for this is that, as shown in FIG. 3, the Vgs-Vds locus passes through the large substrate current region.
Thus, with a conventional circuit there is the problem that there is flow of a large substrate current because of hot carriers and considerable deterioration of the MOS transistor's characteristics occurs. Because of this there is very bad deterioration and a problem of reliability in conventional inverters. This does not just apply to inverters but similarly applies to logic circuits in general. A measure one can think of to counter this is to reduce the above-mentioned substrate current by lowering the power supply voltage from the normal 5 V to 3 V, in order to reduce the high electric field in the vicinity of the drain, but this method finishes by reducing the circuit's operating speed to about 3/5 of what it is with a 5 V power supply. Thus, short channel MOS transistors are deliberately used in order to produce high-speed, large-capacity VLSI circuits, but these initial purposes fail to be achieved because of reliability problems.